1. Field of the Invention
The present invention is directed to the testing of integrated circuits, and more particularly, to the determination of a set of tests for testing integrated circuits.
2. Description of the Background
To ensure a high level of quality of semiconductor devices, a series of tests is performed on the integrated circuits that comprise the devices at various stages in their manufacture. The series of tests ensures that the integrated circuits conform to the performance specifications of the product line which the circuits comprise.
In the manufacture of semiconductor devices, integrated circuits are formed on wafers, which typically contain a number of integrated circuits. The functionality of the integrated circuits is then tested, or probed, while the circuits are still on the wafer. Each wafer is then cut into pieces, or dies, with a diamond saw. Each die represents one integrated circuit. A die that does not pass wafer testing is either discarded or reworked to restore the functionality of the circuits. Dies that pass wafer level testing are usually mounted on a lead frame and encapsulated with a plastic compound to form a semiconductor device. However, the die may be mounted and encapsulated at a later time, after further testing is performed on the die.
Electrical tests are then typically performed on each device. Following this initial testing, burn-in tests are usually performed on each of the devices. Burn-in testing involves testing the devices at high temperatures, usually exceeding 100 degrees Celsius, for a length of time typically exceeding 24 hours. The environmental stress applied to the devices during burn-in testing is much greater than the devices will typically encounter under normal operation. Therefore, burn-in testing identifies defects in the devices that may cause early semiconductor device failures.
Burn-in testing typically cannot test the devices at their maximum operating speeds and cannot perform other discrete tests on the devices. Thus, the devices typically undergo another series of electrical tests. This series of tests is commonly referred to as "final test."
During each of the testing phases, large numbers of electrical tests must be performed on a large number of integrated circuits on wafers or on a large number of packaged semiconductor devices via integrated circuit testers. Due to the large numbers, test times for a production run of a semiconductor device may be long and may thus increase manufacturing costs.
When a new integrated circuit type is introduced to production, it is not known which of these various electrical tests are required to ensure specification compliance. It is typical to run a large number of electrical tests for a period of time (or for a certain number of integrated circuits) to determine which electrical tests are critical. After the initial data are collected, the data are manually reviewed and a reduced set of electrical tests is implemented. This process continues for the life of a product.
A problem associated with the foregoing method is that the calculations must be made according to a large volume of pass/fail data received as a result of a large number of test runs. Thus, the manual calculations are complex and difficult to apply consistently throughout the testing of a product line. Also, the foregoing process of removing tests from the test set has the disadvantage that once a test is removed from the set of applied tests, it is difficult to determine if and when the test should be added back into the test set.
Thus, the need exists for a system and method of determining a set of tests for an integrated circuit. A need also exists for a system and method which performs statistical calculations according to test pass/fail data to determine a set of tests that must be delivered to integrated circuit testers and a system and method which delivers the set of tests to the testers. A need also exists for a system and method that dynamically removes statistically insignificant tests from the test set and adds statistically significant tests into the test set.